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author | Michael Kuperstein <mkuper@google.com> | 2016-08-18 20:08:15 +0000 |
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committer | Michael Kuperstein <mkuper@google.com> | 2016-08-18 20:08:15 +0000 |
commit | 2bc3d4d46c5f19d8433fd088fa95d18f9707bde8 (patch) | |
tree | 1bf251351a4472649c63fb3f1bc7f2f056386f1f /llvm/lib/Target/Mips | |
parent | dea5ccb04b8be312456a5bdb6483cfb0fcb5b962 (diff) | |
download | bcm5719-llvm-2bc3d4d46c5f19d8433fd088fa95d18f9707bde8.tar.gz bcm5719-llvm-2bc3d4d46c5f19d8433fd088fa95d18f9707bde8.zip |
[SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround
The names of the tablegen defs now match the names of the ISD nodes.
This makes the world a slightly saner place, as previously "fround" matched
ISD::FP_ROUND and not ISD::FROUND.
Differential Revision: https://reviews.llvm.org/D23597
llvm-svn: 279129
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index b2b6659ff8d..6bbbd51a638 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -635,9 +635,9 @@ def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; -def : MipsPat<(f32 (fround AFGR64Opnd:$src)), +def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; -def : MipsPat<(f64 (fextend FGR32Opnd:$src)), +def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), (CVT_D32_S FGR32Opnd:$src)>, FGR_32; def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; @@ -657,9 +657,9 @@ def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; -def : MipsPat<(f32 (fround FGR64Opnd:$src)), +def : MipsPat<(f32 (fpround FGR64Opnd:$src)), (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; -def : MipsPat<(f64 (fextend FGR32Opnd:$src)), +def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), (CVT_D64_S FGR32Opnd:$src)>, FGR_64; // Patterns for loads/stores with a reg+imm operand. |