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| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
| commit | 247533179a3e39f78e9da3c7d25093df2b87371c (patch) | |
| tree | 2e31c40e1ed74e452b2f1ff59b04e9c97b082408 /llvm/lib/Target/Mips | |
| parent | 44c9b3758fda7443a201d71925a5b51b1cf4aaf2 (diff) | |
| download | bcm5719-llvm-247533179a3e39f78e9da3c7d25093df2b87371c.tar.gz bcm5719-llvm-247533179a3e39f78e9da3c7d25093df2b87371c.zip | |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
llvm-svn: 133782
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/CMakeLists.txt | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Makefile | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 7 |
3 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt index fd16516f385..f9d953639f4 100644 --- a/llvm/lib/Target/Mips/CMakeLists.txt +++ b/llvm/lib/Target/Mips/CMakeLists.txt @@ -1,8 +1,9 @@ set(LLVM_TARGET_DEFINITIONS Mips.td) -tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header) tablegen(MipsGenRegisterNames.inc -gen-register-enums) -tablegen(MipsGenRegisterInfo.inc -gen-register-desc) +tablegen(MipsGenRegisterDesc.inc -gen-register-desc) +tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header) +tablegen(MipsGenRegisterInfo.inc -gen-register-info) tablegen(MipsGenInstrNames.inc -gen-instr-enums) tablegen(MipsGenInstrInfo.inc -gen-instr-desc) tablegen(MipsGenAsmWriter.inc -gen-asm-writer) diff --git a/llvm/lib/Target/Mips/Makefile b/llvm/lib/Target/Mips/Makefile index d16b066a624..d7eab61a72e 100644 --- a/llvm/lib/Target/Mips/Makefile +++ b/llvm/lib/Target/Mips/Makefile @@ -13,7 +13,8 @@ TARGET = Mips # Make sure that tblgen is run, first thing. BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \ - MipsGenRegisterInfo.inc MipsGenInstrNames.inc \ + MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \ + MipsGenInstrNames.inc \ MipsGenInstrInfo.inc MipsGenAsmWriter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtarget.inc diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index fa64f637c8e..6fdcf45e655 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -35,12 +35,15 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" +#include "MipsGenRegisterDesc.inc" +#include "MipsGenRegisterInfo.inc" using namespace llvm; MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, const TargetInstrInfo &tii) - : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), + : MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc, + Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), Subtarget(ST), TII(tii) {} /// getRegisterNumbering - Given the enum value for some register, e.g. @@ -285,5 +288,3 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const { int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); } - -#include "MipsGenRegisterInfo.inc" |
