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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-11-08 21:21:00 -0800
committerMatt Arsenault <arsenm2@gmail.com>2020-01-03 16:25:10 -0500
commit21309eafdebaa0041a83a026ae011e305b2f52a0 (patch)
tree90e6cbd12199a7b12155ca8a6b2a404bc4e4dca6 /llvm/lib/Target/Mips
parent555fc92a85914c2bcccbc01886039284c4f9db57 (diff)
downloadbcm5719-llvm-21309eafdebaa0041a83a026ae011e305b2f52a0.tar.gz
bcm5719-llvm-21309eafdebaa0041a83a026ae011e305b2f52a0.zip
GlobalISel: Add type argument to getRegBankFromRegClass
AMDGPU can't unambiguously go back from the selected instruction register class to the register bank without knowing if this was used in a boolean context.
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp5
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterBankInfo.h4
2 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 272fe9a8dd2..2a3f5a05dfe 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -76,8 +76,9 @@ using namespace llvm;
MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
: MipsGenRegisterBankInfo() {}
-const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
- const TargetRegisterClass &RC) const {
+const RegisterBank &
+MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
+ LLT) const {
using namespace Mips;
switch (RC.getID()) {
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.h b/llvm/lib/Target/Mips/MipsRegisterBankInfo.h
index fa0f1c7bc94..66267f8d794 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.h
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.h
@@ -32,8 +32,8 @@ class MipsRegisterBankInfo final : public MipsGenRegisterBankInfo {
public:
MipsRegisterBankInfo(const TargetRegisterInfo &TRI);
- const RegisterBank &
- getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
+ const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
+ LLT) const override;
const InstructionMapping &
getInstrMapping(const MachineInstr &MI) const override;
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