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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-07-10 13:38:23 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-07-10 13:38:23 +0000 |
commit | 7e527423f54f413ae304900ee4b3ef4a17cd4fb1 (patch) | |
tree | cf77e01985054a64bd2715c0ff8f203cadac4511 /llvm/lib/Target/Mips/MipsTargetStreamer.h | |
parent | cad431c122ea678344ac465c5bce626720dcc94e (diff) | |
download | bcm5719-llvm-7e527423f54f413ae304900ee4b3ef4a17cd4fb1.tar.gz bcm5719-llvm-7e527423f54f413ae304900ee4b3ef4a17cd4fb1.zip |
[mips] Add support for -modd-spreg/-mno-odd-spreg
Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.
This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
instructions to/from odd registers are guaranteed not to appear for any
reason. Once this has been established, the user can then re-enable
-modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
O32 FP64A is used as the ABI. This is intended to provide almost all
functionality of an FR=1 processor but can also be executed on a FR=0 core
with the assistance of a hardware compatibility mode which emulates FR=0
behaviour on an FR=1 processor.
* Added '.module oddspreg' and '.module nooddspreg' each of which update
the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
than trying to maintain them in the same format they will be emitted in.
There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.
Differential Revision: http://reviews.llvm.org/D4383
llvm-svn: 212717
Diffstat (limited to 'llvm/lib/Target/Mips/MipsTargetStreamer.h')
-rw-r--r-- | llvm/lib/Target/Mips/MipsTargetStreamer.h | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MipsTargetStreamer.h b/llvm/lib/Target/Mips/MipsTargetStreamer.h index 18434116f39..99f7d4c92cf 100644 --- a/llvm/lib/Target/Mips/MipsTargetStreamer.h +++ b/llvm/lib/Target/Mips/MipsTargetStreamer.h @@ -18,8 +18,6 @@ namespace llvm { struct MipsABIFlagsSection; -typedef MipsABIFlagsSection::Val_GNU_MIPS_ABI Val_GNU_MIPS_ABI; - class MipsTargetStreamer : public MCTargetStreamer { public: MipsTargetStreamer(MCStreamer &S); @@ -56,11 +54,23 @@ public: virtual void emitDirectiveCpload(unsigned RegNo); virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg); - // ABI Flags - virtual void emitDirectiveModuleFP(Val_GNU_MIPS_ABI Value, bool Is32BitAbi) { - ABIFlagsSection.FpABI = Value; + + /// Emit a '.module fp=value' directive using the given values. + /// Updates the .MIPS.abiflags section + virtual void emitDirectiveModuleFP(MipsABIFlagsSection::FpABIKind Value, + bool Is32BitABI) { + ABIFlagsSection.setFpABI(Value, Is32BitABI); } - virtual void emitDirectiveSetFp(Val_GNU_MIPS_ABI Value, bool Is32BitAbi){}; + + /// Emit a '.module fp=value' directive using the current values of the + /// .MIPS.abiflags section. + void emitDirectiveModuleFP() { + emitDirectiveModuleFP(ABIFlagsSection.getFpABI(), + ABIFlagsSection.Is32BitABI); + } + + virtual void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI); + virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value){}; virtual void emitMipsAbiFlags(){}; void setCanHaveModuleDir(bool Can) { canHaveModuleDirective = Can; } bool getCanHaveModuleDir() { return canHaveModuleDirective; } @@ -122,8 +132,10 @@ public: const MCSymbol &Sym, bool IsReg) override; // ABI Flags - void emitDirectiveModuleFP(Val_GNU_MIPS_ABI Value, bool Is32BitAbi) override; - void emitDirectiveSetFp(Val_GNU_MIPS_ABI Value, bool Is32BitAbi) override; + void emitDirectiveModuleFP(MipsABIFlagsSection::FpABIKind Value, + bool Is32BitABI) override; + void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override; + void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override; void emitMipsAbiFlags() override; }; @@ -177,6 +189,7 @@ public: const MCSymbol &Sym, bool IsReg) override; // ABI Flags + void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override; void emitMipsAbiFlags() override; protected: |