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authorDaniel Sanders <daniel.sanders@imgtec.com>2015-09-03 12:31:22 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2015-09-03 12:31:22 +0000
commit3ebcaf6685cb03a40bde5f2773c4ef672b6ce56b (patch)
tree2ab96852b7ed1f2a293f64022866e68fd1c130d1 /llvm/lib/Target/Mips/MipsSubtarget.h
parent8d01772dae2219e7f40359c06c4b83e8c20a22bd (diff)
downloadbcm5719-llvm-3ebcaf6685cb03a40bde5f2773c4ef672b6ce56b.tar.gz
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[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler.
Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.h')
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 7a4a8932c62..9fc8ec6b3e3 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -130,6 +130,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// HasMSA -- supports MSA ASE.
bool HasMSA;
+ // UseTCCInDIV -- Enables the use of trapping in the assembler.
+ bool UseTCCInDIV;
+
InstrItineraryData InstrItins;
// We can override the determination of whether we are in mips16 mode
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