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authorSimon Dardis <simon.dardis@imgtec.com>2017-07-11 18:03:20 +0000
committerSimon Dardis <simon.dardis@imgtec.com>2017-07-11 18:03:20 +0000
commitae719c5a17854f861bb5b74b0a861d402ba5668c (patch)
treebb1c4124206b3cf25b46de2c67b2750fe0c6a044 /llvm/lib/Target/Mips/MipsSubtarget.cpp
parent94b3b47c73c6c1191c27823a0a5bbb5a020767bf (diff)
downloadbcm5719-llvm-ae719c5a17854f861bb5b74b0a861d402ba5668c.tar.gz
bcm5719-llvm-ae719c5a17854f861bb5b74b0a861d402ba5668c.zip
[mips][mt][1/7] Add the MT ASE as a subtarget feature.
Preparatory work for adding the MIPS MT (multi-threading) ASE instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35247 llvm-svn: 307679
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 154d5825427..eba21e0a1c6 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -70,7 +70,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
- HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(),
+ HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM),
+ TargetTriple(TT), TSInfo(),
InstrInfo(
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
FrameLowering(MipsFrameLowering::create(*this)),
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