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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-27 16:42:17 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-27 16:42:17 +0000 |
| commit | 5e94e68f7b2d2c97dd465137de6ca6024f08265a (patch) | |
| tree | dfa24a21bbbc63dc855646f1b0e63d6c042e151c /llvm/lib/Target/Mips/MipsSubtarget.cpp | |
| parent | ef099dc670f2157fbd1ce21559603ceb23201f6e (diff) | |
| download | bcm5719-llvm-5e94e68f7b2d2c97dd465137de6ca6024f08265a.tar.gz bcm5719-llvm-5e94e68f7b2d2c97dd465137de6ca6024f08265a.zip | |
[mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR's
Summary:
No functional change since these predicates are (currently) synonymous.
Extracted from a patch by David Chisnall
His work was sponsored by: DARPA, AFRL
Differential Revision: http://llvm-reviews.chandlerc.com/D3202
llvm-svn: 204943
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSubtarget.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index b0565f80026..143b94599b2 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -117,8 +117,8 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1); // Check if Architecture and ABI are compatible. - assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) || - (hasMips64() && (isABI_N32() || isABI_N64()))) && + assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || + (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); if (hasMSA() && !isFP64bit()) @@ -143,8 +143,8 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, RegClassVector &CriticalPathRCs) const { Mode = TargetSubtargetInfo::ANTIDEP_NONE; CriticalPathRCs.clear(); - CriticalPathRCs.push_back(hasMips64() ? - &Mips::GPR64RegClass : &Mips::GPR32RegClass); + CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass + : &Mips::GPR32RegClass); return OptLevel >= CodeGenOpt::Aggressive; } |
