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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-27 16:42:17 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-27 16:42:17 +0000 |
| commit | 5e94e68f7b2d2c97dd465137de6ca6024f08265a (patch) | |
| tree | dfa24a21bbbc63dc855646f1b0e63d6c042e151c /llvm/lib/Target/Mips/MipsSEISelLowering.cpp | |
| parent | ef099dc670f2157fbd1ce21559603ceb23201f6e (diff) | |
| download | bcm5719-llvm-5e94e68f7b2d2c97dd465137de6ca6024f08265a.tar.gz bcm5719-llvm-5e94e68f7b2d2c97dd465137de6ca6024f08265a.zip | |
[mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR's
Summary:
No functional change since these predicates are (currently) synonymous.
Extracted from a patch by David Chisnall
His work was sponsored by: DARPA, AFRL
Differential Revision: http://llvm-reviews.chandlerc.com/D3202
llvm-svn: 204943
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 0435d278e76..218cd15baa9 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -38,7 +38,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) // Set up the register classes addRegisterClass(MVT::i32, &Mips::GPR32RegClass); - if (hasMips64()) + if (isGP64bit()) addRegisterClass(MVT::i64, &Mips::GPR64RegClass); if (Subtarget->hasDSP() || Subtarget->hasMSA()) { |
