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| author | Simon Dardis <simon.dardis@mips.com> | 2017-11-02 12:47:22 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2017-11-02 12:47:22 +0000 |
| commit | 725acb2d91e4aa9fca1c97760c81f3443549626c (patch) | |
| tree | 226433d9f13ac27a9f61784f3485485c3994b0e4 /llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | |
| parent | 0e142499a97a16c34b934aeb6ca186ae81a230e2 (diff) | |
| download | bcm5719-llvm-725acb2d91e4aa9fca1c97760c81f3443549626c.tar.gz bcm5719-llvm-725acb2d91e4aa9fca1c97760c81f3443549626c.zip | |
[mips] Use register scavenging with MSA.
MSA stores and loads to the stack are more likely to require an
emergency GPR spill slot due to the smaller offsets available
with those instructions.
Handle this by overestimating the size of the stack by determining
the largest offset presuming that all callee save registers are
spilled and accounting of incoming arguments when determining
whether an emergency spill slot is required.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D39056
llvm-svn: 317204
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index 0b19b18449e..ca19089c912 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -893,10 +893,12 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, } // Set scavenging frame index if necessary. - uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() + - estimateStackSize(MF); + uint64_t MaxSPOffset = estimateStackSize(MF); - if (isInt<16>(MaxSPOffset)) + // MSA has a minimum offset of 10 bits signed. If there is a variable + // sized object on the stack, the estimation cannot account for it. + if (isIntN(STI.hasMSA() ? 10 : 16, MaxSPOffset) && + !MF.getFrameInfo().hasVarSizedObjects()) return; const TargetRegisterClass &RC = |

