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author | Eric Christopher <echristo@gmail.com> | 2015-01-29 23:27:36 +0000 |
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committer | Eric Christopher <echristo@gmail.com> | 2015-01-29 23:27:36 +0000 |
commit | 96e72c6ab168914d2323e15579a2593edb8b6515 (patch) | |
tree | 090851819b44d9f22277657efbc3dc502f23c73a /llvm/lib/Target/Mips/MipsRegisterInfo.cpp | |
parent | e4b705bc1cc6140ded88c3ac685f4398b80888d0 (diff) | |
download | bcm5719-llvm-96e72c6ab168914d2323e15579a2593edb8b6515.tar.gz bcm5719-llvm-96e72c6ab168914d2323e15579a2593edb8b6515.zip |
Remove most of the TargetMachine::getSubtarget/getSubtargetImpl
calls that don't take a Function argument from Mips. Notable
exceptions: the AsmPrinter and MipsTargetObjectFile. The
latter needs to be fixed, and the former will be fixed when the
general AsmPrinter changes happen.
llvm-svn: 227512
Diffstat (limited to 'llvm/lib/Target/Mips/MipsRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 20ef3f387dc..2110c031c23 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -17,6 +17,7 @@ #include "MipsInstrInfo.h" #include "MipsMachineFunction.h" #include "MipsSubtarget.h" +#include "MipsTargetMachine.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -62,7 +63,7 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case Mips::GPR32RegClassID: case Mips::GPR64RegClassID: case Mips::DSPRRegClassID: { - const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); return 28 - TFI->hasFP(MF); } case Mips::FGR32RegClassID: @@ -167,7 +168,7 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(*Reg); } // Reserve FP if this function should have a dedicated frame pointer register. - if (MF.getSubtarget().getFrameLowering()->hasFP(MF)) { + if (Subtarget.getFrameLowering()->hasFP(MF)) { if (Subtarget.inMips16Mode()) Reserved.set(Mips::S0); else { @@ -256,8 +257,9 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned MipsRegisterInfo:: getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - bool IsN64 = Subtarget.isABI_N64(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + bool IsN64 = + static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64(); if (Subtarget.inMips16Mode()) return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; |