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authorPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-03-25 11:38:06 +0000
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-03-25 11:38:06 +0000
commita034a64f842020a90a3b508f3c3e5c8d572fd701 (patch)
tree0ca1ea70a8b6c46eb4412826109b989b8bd318fe /llvm/lib/Target/Mips/MipsInstructionSelector.cpp
parent3d9fa09aa280d7cb03a9388fca4d7838215ed382 (diff)
downloadbcm5719-llvm-a034a64f842020a90a3b508f3c3e5c8d572fd701.tar.gz
bcm5719-llvm-a034a64f842020a90a3b508f3c3e5c8d572fd701.zip
[MIPS GlobalISel] Select copy for arguments from FPRBRegBank
Move selectCopy into MipsInstructionSelector class. Select copy for arguments from FPRBRegBank for MIPS32. Differential Revision: https://reviews.llvm.org/D59644 llvm-svn: 356886
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstructionSelector.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsInstructionSelector.cpp20
1 files changed, 15 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 36aea298359..ded8c1c1fbc 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -38,6 +38,7 @@ private:
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
bool materialize32BitImm(unsigned DestReg, APInt Imm,
MachineIRBuilder &B) const;
+ bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
const MipsTargetMachine &TM;
const MipsSubtarget &STI;
@@ -75,15 +76,24 @@ MipsInstructionSelector::MipsInstructionSelector(
{
}
-static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
- MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
- const RegisterBankInfo &RBI) {
+bool MipsInstructionSelector::selectCopy(MachineInstr &I,
+ MachineRegisterInfo &MRI) const {
unsigned DstReg = I.getOperand(0).getReg();
if (TargetRegisterInfo::isPhysicalRegister(DstReg))
return true;
- const TargetRegisterClass *RC = &Mips::GPR32RegClass;
+ const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
+ const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
+ const TargetRegisterClass *RC = &Mips::GPR32RegClass;
+ if (RegBank->getID() == Mips::FPRBRegBankID) {
+ if (DstSize == 32)
+ RC = &Mips::FGR32RegClass;
+ else if (DstSize == 64)
+ RC = STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
+ else
+ llvm_unreachable("Unsupported destination size");
+ }
if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
<< " operand\n");
@@ -162,7 +172,7 @@ bool MipsInstructionSelector::select(MachineInstr &I,
if (!isPreISelGenericOpcode(I.getOpcode())) {
if (I.isCopy())
- return selectCopy(I, TII, MRI, TRI, RBI);
+ return selectCopy(I, MRI);
return true;
}
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