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authorPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-01-24 10:27:21 +0000
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>2019-01-24 10:27:21 +0000
commit79df859685de2a0ad00d03f2060fae760d66827b (patch)
tree9de38a1b0299c86ae78e4c34bb87670a313c6fec /llvm/lib/Target/Mips/MipsInstructionSelector.cpp
parentb5a939d24653183947d5261f49609cc7c9ed1873 (diff)
downloadbcm5719-llvm-79df859685de2a0ad00d03f2060fae760d66827b.tar.gz
bcm5719-llvm-79df859685de2a0ad00d03f2060fae760d66827b.zip
[MIPS GlobalISel] Select zero extending and sign extending load
Select zero extending and sign extending load for MIPS32. Use size from MachineMemOperand to determine number of bytes to load. Differential Revision: https://reviews.llvm.org/D57099 llvm-svn: 352038
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstructionSelector.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsInstructionSelector.cpp32
1 files changed, 30 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 37d7767085a..eb8c919d38c 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -90,6 +90,28 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
return true;
}
+/// Returning Opc indicates that we failed to select MIPS instruction opcode.
+static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
+ if (Opc == TargetOpcode::G_STORE)
+ switch (MemSizeInBytes) {
+ case 4:
+ return Mips::SW;
+ default:
+ return Opc;
+ }
+ else
+ switch (MemSizeInBytes) {
+ case 4:
+ return Mips::LW;
+ case 2:
+ return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
+ case 1:
+ return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
+ default:
+ return Opc;
+ }
+}
+
bool MipsInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
@@ -127,15 +149,21 @@ bool MipsInstructionSelector::select(MachineInstr &I,
break;
}
case G_STORE:
- case G_LOAD: {
+ case G_LOAD:
+ case G_ZEXTLOAD:
+ case G_SEXTLOAD: {
const unsigned DestReg = I.getOperand(0).getReg();
const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
+ const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
return false;
- const unsigned NewOpc = I.getOpcode() == G_STORE ? Mips::SW : Mips::LW;
+ const unsigned NewOpc =
+ selectLoadStoreOpCode(I.getOpcode(), OpMemSizeInBytes);
+ if (NewOpc == I.getOpcode())
+ return false;
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
.add(I.getOperand(0))
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