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| author | Petar Jovanovic <petar.jovanovic@mips.com> | 2018-05-17 16:30:32 +0000 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@mips.com> | 2018-05-17 16:30:32 +0000 |
| commit | daf5169398e7605c68d61c21618e887ce4980931 (patch) | |
| tree | a5f750d7f673179cf20d42a03253e2f73c95f24c /llvm/lib/Target/Mips/MipsInstrInfo.td | |
| parent | bd332588bd3997fec40447c9bc98706085145b3c (diff) | |
| download | bcm5719-llvm-daf5169398e7605c68d61c21618e887ce4980931.tar.gz bcm5719-llvm-daf5169398e7605c68d61c21618e887ce4980931.zip | |
[mips] Add support for Global INValidate ASE
This includes
Instructions: ginvi, ginvt,
Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv
Attribute: ginv
.MIPS.abiflags: GINV (0x20000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D46268
llvm-svn: 332624
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index cdcf997ff8e..2a7f5404e43 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -252,6 +252,8 @@ def HasCRC : Predicate<"Subtarget->hasCRC()">, AssemblerPredicate<"FeatureCRC">; def HasVirt : Predicate<"Subtarget->hasVirt()">, AssemblerPredicate<"FeatureVirt">; +def HasGINV : Predicate<"Subtarget->hasGINV()">, + AssemblerPredicate<"FeatureGINV">; // TODO: Add support for FPOpFusion::Standard def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion ==" " FPOpFusion::Fast">; @@ -468,6 +470,10 @@ class ASE_VIRT { list <Predicate> ASEPredicate = [HasVirt]; } +class ASE_GINV { + list <Predicate> ASEPredicate = [HasGINV]; +} + // Class used for separating microMIPSr6 and microMIPS (r3) instruction. // It can be used only on instructions that doesn't inherit PredicateControl. class ISA_MICROMIPS_NOT_32R6 : PredicateControl { |
