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| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-07-11 07:41:56 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-07-11 07:41:56 +0000 |
| commit | cba9f80ba87610b5f46f1baccbad548f2f15f0c6 (patch) | |
| tree | 411fa795b35aae5c553f76318cae14e0cde3c0a0 /llvm/lib/Target/Mips/MipsInstrInfo.td | |
| parent | 4d61a3c2d8864bec52e4d2ca700cbbbc10e5797f (diff) | |
| download | bcm5719-llvm-cba9f80ba87610b5f46f1baccbad548f2f15f0c6.tar.gz bcm5719-llvm-cba9f80ba87610b5f46f1baccbad548f2f15f0c6.zip | |
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D18824
llvm-svn: 275050
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 0d7abbf7b9f..296f6e9b08b 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1742,9 +1742,10 @@ let AdditionalPredicates = [NotInMicroMips] in { /// Load and Store Instructions /// aligned -def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; -def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, - LW_FM<0x24>; +def LB : LoadMemory<"lb", GPR32Opnd, mem_simm16, sextloadi8, II_LB>, MMRel, + LW_FM<0x20>; +def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simm16, zextloadi8, II_LBU, + addrDefault>, MMRel, LW_FM<0x24>; let AdditionalPredicates = [NotInMicroMips] in { def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, addrDefault>, MMRel, LW_FM<0x21>; @@ -1775,14 +1776,14 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, let AdditionalPredicates = [NotInMicroMips] in { // COP2 Memory Instructions -def LWC2 : LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>, +def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>, ISA_MIPS1_NOT_32R6_64R6; -def SWC2 : SW_FT2<"swc2", COP2Opnd, II_SWC2, store>, LW_FM<0x3a>, - ISA_MIPS1_NOT_32R6_64R6; -def LDC2 : LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>, - ISA_MIPS2_NOT_32R6_64R6; -def SDC2 : SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>, LW_FM<0x3e>, +def SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, II_SWC2, store>, + LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6; +def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>, ISA_MIPS2_NOT_32R6_64R6; +def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>, + LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6; // COP3 Memory Instructions let DecoderNamespace = "COP3_" in { |
