[mips] Implement Octeon+ `saa` and `saad` instructions

`saa` and `saad` are 32-bit and 64-bit store atomic add instructions.

   memory[base] = memory[base] + rt

These instructions are available for "Octeon+" CPU. The patch adds support
for both instructions to MIPS assembler and diassembler and introduces new
CPU type - "octeon+".

Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP`
ISA extension flag support.

Differential Revision: https://reviews.llvm.org/D69849

1 files changed, 12 insertions, 0 deletions

diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index a1e245f5303..b560da8cc71 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -211,6 +211,10 @@ def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
                       AssemblerPredicate<"FeatureCnMips">;
 def NotCnMips    :    Predicate<"!Subtarget->hasCnMips()">,
                       AssemblerPredicate<"!FeatureCnMips">;
+def HasCnMipsP   :    Predicate<"Subtarget->hasCnMipsP()">,
+                      AssemblerPredicate<"FeatureCnMipsP">;
+def NotCnMipsP   :    Predicate<"!Subtarget->hasCnMipsP()">,
+                      AssemblerPredicate<"!FeatureCnMipsP">;
 def IsSym32     :     Predicate<"Subtarget->hasSym32()">,
                       AssemblerPredicate<"FeatureSym32">;
 def IsSym64     :     Predicate<"!Subtarget->hasSym32()">,
@@ -439,6 +443,14 @@ class NOT_ASE_CNMIPS {
   list<Predicate> ASEPredicate = [NotCnMips];
 }
 
+class ASE_CNMIPSP {
+  list<Predicate> ASEPredicate = [HasCnMipsP];
+}
+
+class NOT_ASE_CNMIPSP {
+  list<Predicate> ASEPredicate = [NotCnMipsP];
+}
+
 class ASE_MIPS64_CNMIPS {
   list<Predicate> ASEPredicate = [HasMips64, HasCnMips];
 }