diff options
| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-22 10:55:05 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-22 10:55:05 +0000 |
| commit | 437153bb8022f55c0574760400407e449aeb1dd0 (patch) | |
| tree | b9d38240a9da9cc72866e5e350de42f3cc382397 /llvm/lib/Target/Mips/MipsInstrInfo.td | |
| parent | 4162d77744b2e181f2db619b76fc112b59c2ef13 (diff) | |
| download | bcm5719-llvm-437153bb8022f55c0574760400407e449aeb1dd0.tar.gz bcm5719-llvm-437153bb8022f55c0574760400407e449aeb1dd0.zip | |
[mips] Correct the predicates of the cache and pref instructions
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46949
llvm-svn: 332970
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 2a7f5404e43..f78b9931065 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2454,10 +2454,12 @@ class CacheOp<string instr_asm, Operand MemOpnd, let DecoderMethod = "DecodeCacheOp"; } -def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>, - INSN_MIPS3_32_NOT_32R6_64R6; -def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>, - INSN_MIPS3_32_NOT_32R6_64R6; +let AdditionalPredicates = [NotInMicroMips] in { + def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>, + INSN_MIPS3_32_NOT_32R6_64R6; + def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>, + INSN_MIPS3_32_NOT_32R6_64R6; +} // FIXME: We are missing the prefx instruction. def ROL : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), |
