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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-11-21 20:30:41 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-11-21 20:30:41 +0000 |
| commit | 43115a1ce4e70ec1738a044ba18173ca210f1322 (patch) | |
| tree | 92032b1432956e998fa96f95f4738de4edb6dfbd /llvm/lib/Target/Mips/MipsInstrInfo.td | |
| parent | d559da84af3bb8087cece160e0ab89bdacb9b30e (diff) | |
| download | bcm5719-llvm-43115a1ce4e70ec1738a044ba18173ca210f1322.tar.gz bcm5719-llvm-43115a1ce4e70ec1738a044ba18173ca210f1322.zip | |
[mips] seq macro support
This patch adds the seq macro.
This partially resolves PR/30381.
Thanks to Sean Bruno for reporting the issue!
Reviewers: zoran.jovanovic, vkalintiris, seanbruno
Differential Revision: https://reviews.llvm.org/D24607
llvm-svn: 287573
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 22060dfc70e..1c825b442d0 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -203,6 +203,8 @@ def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, AssemblerPredicate<"FeatureMips16">; def HasCnMips : Predicate<"Subtarget->hasCnMips()">, AssemblerPredicate<"FeatureCnMips">; +def NotCnMips : Predicate<"!Subtarget->hasCnMips()">, + AssemblerPredicate<"!FeatureCnMips">; def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; def RelocPIC : Predicate<"TM.isPositionIndependent()">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; @@ -335,6 +337,10 @@ class ASE_CNMIPS { list<Predicate> InsnPredicates = [HasCnMips]; } +class NOT_ASE_CNMIPS { + list<Predicate> InsnPredicates = [NotCnMips]; +} + class ASE_MIPS64_CNMIPS { list<Predicate> InsnPredicates = [HasMips64, HasCnMips]; } @@ -2260,6 +2266,21 @@ def : MipsInstAlias<"dror $rd, $imm", def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), "abs\t$rd, $rs">; +def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, GPR32Opnd:$rt), + "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS; + +def : MipsInstAlias<"seq $rd, $rs", + (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, + NOT_ASE_CNMIPS; + +def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, simm32_relaxed:$imm), + "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS; + +def : MipsInstAlias<"seq $rd, $imm", + (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, + NOT_ASE_CNMIPS; //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// |
