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| author | Simon Dardis <simon.dardis@imgtec.com> | 2017-01-31 10:49:24 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2017-01-31 10:49:24 +0000 |
| commit | 12850eeac5dbd1dee229044ba75f27e2d4c44d78 (patch) | |
| tree | 27f3dcc72b4ae5e113223ca4fb81a5330be83848 /llvm/lib/Target/Mips/MipsInstrInfo.td | |
| parent | 0c0789bc3f4cf36bd2f86e8c4a9e41e7992e7383 (diff) | |
| download | bcm5719-llvm-12850eeac5dbd1dee229044ba75f27e2d4c44d78.tar.gz bcm5719-llvm-12850eeac5dbd1dee229044ba75f27e2d4c44d78.zip | |
[mips] Addition of the immediate cases for the instructions [d]div, [d]divu
Related to http://reviews.llvm.org/D15772
Depends on http://reviews.llvm.org/D16888
Adds support for immediate operand for [D]DIV[U] instructions.
Patch By: Srdjan Obucina
Reviewers: zoran.jovanovic, vkalintiris, dsanders, obucina
Differential Revision: https://reviews.llvm.org/D16889
llvm-svn: 293614
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 883dac3549f..fc2586761f4 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2561,30 +2561,58 @@ def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), "div\t$rd, $rs, $rt">, ISA_MIPS1_NOT_32R6_64R6; +def SDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, simm32:$imm), + "div\t$rd, $rs, $imm">, + ISA_MIPS1_NOT_32R6_64R6; def UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), "divu\t$rd, $rs, $rt">, ISA_MIPS1_NOT_32R6_64R6; +def UDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, simm32:$imm), + "divu\t$rd, $rs, $imm">, + ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"div $rd, $imm", (SDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, + simm32:$imm), 0>, + ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, + simm32:$imm), 0>, + ISA_MIPS1_NOT_32R6_64R6; def DSDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), "ddiv\t$rd, $rs, $rt">, ISA_MIPS64_NOT_64R6; +def DSDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, imm64:$imm), + "ddiv\t$rd, $rs, $imm">, + ISA_MIPS64_NOT_64R6; def DUDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), "ddivu\t$rd, $rs, $rt">, ISA_MIPS64_NOT_64R6; +def DUDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, imm64:$imm), + "ddivu\t$rd, $rs, $imm">, + ISA_MIPS64_NOT_64R6; def : MipsInstAlias<"ddiv $rt, $rs", (DSDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS64_NOT_64R6; +def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, + imm64:$imm), 0>, + ISA_MIPS64_NOT_64R6; def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS64_NOT_64R6; +def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR32Opnd:$rd, + GPR32Opnd:$rd, imm64:$imm), + 0>, ISA_MIPS64_NOT_64R6; def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; |
