diff options
| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-15 11:10:30 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-15 11:10:30 +0000 |
| commit | b79ecec20d564a60c9ff8f4ac5994594e96701ea (patch) | |
| tree | 28eac65be3be9fa230bde9aa6eead08b875d46c1 /llvm/lib/Target/Mips/MipsInstrFPU.td | |
| parent | 761c2247b44a4128e715fe71a1faeadd28d4028a (diff) | |
| download | bcm5719-llvm-b79ecec20d564a60c9ff8f4ac5994594e96701ea.tar.gz bcm5719-llvm-b79ecec20d564a60c9ff8f4ac5994594e96701ea.zip | |
[mips] Fix predicates of mfc1, mtc1 instructions
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46692
llvm-svn: 332339
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 3b4e4966725..96e5457952a 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -478,37 +478,34 @@ let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in { def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; -} -def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, - bitconvert>, MFC1_FM<0>; -def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, - FGR_64 { - let DecoderNamespace = "MipsFP64"; -} -def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, - bitconvert>, MFC1_FM<4>; -def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, - FGR_64 { - let DecoderNamespace = "MipsFP64"; -} -let AdditionalPredicates = [NotInMicroMips] in { + def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, + bitconvert>, MFC1_FM<0>; + def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, + FGR_64 { + let DecoderNamespace = "MipsFP64"; + } + def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, + bitconvert>, MFC1_FM<4>; + def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, + FGR_64 { + let DecoderNamespace = "MipsFP64"; + } + def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, MFC1_FM<3>, ISA_MIPS32R2, FGR_32; def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { let DecoderNamespace = "MipsFP64"; } -} -let AdditionalPredicates = [NotInMicroMips] in { + def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, MFC1_FM<7>, ISA_MIPS32R2, FGR_32; def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { let DecoderNamespace = "MipsFP64"; } -} -let AdditionalPredicates = [NotInMicroMips] in { + def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, bitconvert>, MFC1_FM<5>, ISA_MIPS3; def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, |
