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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-27 16:42:17 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-27 16:42:17 +0000 |
| commit | 5e94e68f7b2d2c97dd465137de6ca6024f08265a (patch) | |
| tree | dfa24a21bbbc63dc855646f1b0e63d6c042e151c /llvm/lib/Target/Mips/MipsISelLowering.cpp | |
| parent | ef099dc670f2157fbd1ce21559603ceb23201f6e (diff) | |
| download | bcm5719-llvm-5e94e68f7b2d2c97dd465137de6ca6024f08265a.tar.gz bcm5719-llvm-5e94e68f7b2d2c97dd465137de6ca6024f08265a.zip | |
[mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR's
Summary:
No functional change since these predicates are (currently) synonymous.
Extracted from a patch by David Chisnall
His work was sponsored by: DARPA, AFRL
Differential Revision: http://llvm-reviews.chandlerc.com/D3202
llvm-svn: 204943
Diffstat (limited to 'llvm/lib/Target/Mips/MipsISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 13de7e3a577..11eee42946c 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3029,9 +3029,9 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const return std::make_pair(0U, &Mips::CPU16RegsRegClass); return std::make_pair(0U, &Mips::GPR32RegClass); } - if (VT == MVT::i64 && !hasMips64()) + if (VT == MVT::i64 && !isGP64bit()) return std::make_pair(0U, &Mips::GPR32RegClass); - if (VT == MVT::i64 && hasMips64()) + if (VT == MVT::i64 && isGP64bit()) return std::make_pair(0U, &Mips::GPR64RegClass); // This will generate an error message return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); |
