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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-26 20:13:47 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-26 20:13:47 +0000 |
| commit | 1fb1b8b811afd237198577e12d39b3a532c97422 (patch) | |
| tree | 20a52077e5a37dc5b140f128018bb4cc6fa3d201 /llvm/lib/Target/Mips/MipsISelLowering.cpp | |
| parent | cc4e4d80fe58c89f48ffe29f24e286ea38f241bf (diff) | |
| download | bcm5719-llvm-1fb1b8b811afd237198577e12d39b3a532c97422.tar.gz bcm5719-llvm-1fb1b8b811afd237198577e12d39b3a532c97422.zip | |
[mips] Fix FP branch instructions to have explicit FP condition code register
operands.
llvm-svn: 187238
Diffstat (limited to 'llvm/lib/Target/Mips/MipsISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index ffa077fe5da..10efc8adea2 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -1438,8 +1438,9 @@ lowerBRCOND(SDValue Op, SelectionDAG &DAG) const (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; SDValue BrCode = DAG.getConstant(Opc, MVT::i32); + SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, - Dest, CondRes); + FCC0, Dest, CondRes); } SDValue MipsTargetLowering:: |
