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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-09 09:22:52 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-09 09:22:52 +0000 |
| commit | 8efa9790290d29931df95056b5b76fc0c3373e73 (patch) | |
| tree | e24e736dbc99762d1c3902e1bb3c35b8a2d6366c /llvm/lib/Target/Mips/MipsFastISel.cpp | |
| parent | ddad6e028ec3f348fab624988d6ad1d4c1316f3e (diff) | |
| download | bcm5719-llvm-8efa9790290d29931df95056b5b76fc0c3373e73.tar.gz bcm5719-llvm-8efa9790290d29931df95056b5b76fc0c3373e73.zip | |
[mips] Fix c.<cc>.<fmt> instruction definition.
As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.
Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.
Reviewers: dsanders, vkalintiris, zoran.jovanovic
Differential Review: https://reviews.llvm.org/D23118
llvm-svn: 281022
Diffstat (limited to 'llvm/lib/Target/Mips/MipsFastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsFastISel.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 94531642492..58a53a07937 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -709,8 +709,10 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) { unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); - emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( - Mips::FCC0, RegState::ImplicitDefine); + emitInst(Opc) + .addReg(Mips::FCC0, RegState::Define) + .addReg(LeftReg) + .addReg(RightReg); emitInst(CondMovOpc, ResultReg) .addReg(RegWithOne) .addReg(Mips::FCC0) |
