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authorDuncan P. N. Exon Smith <dexonsmith@apple.com>2016-07-12 01:47:02 +0000
committerDuncan P. N. Exon Smith <dexonsmith@apple.com>2016-07-12 01:47:02 +0000
commitfdd30c620da25a98c7cae6e413577ac7534fa9e0 (patch)
tree3e334f5e0640bee952704090f7bd32fc048c80ad /llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
parent185ab5b030bab551669df712ce410aa087471d86 (diff)
downloadbcm5719-llvm-fdd30c620da25a98c7cae6e413577ac7534fa9e0.tar.gz
bcm5719-llvm-fdd30c620da25a98c7cae6e413577ac7534fa9e0.zip
Mips: Avoid implicit iterator conversions, NFC
Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the Mips backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable and using range-based for loops. llvm-svn: 275141
Diffstat (limited to 'llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 76361b85bf4..5ec1717e48a 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -600,9 +600,9 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
if (Filled) {
// Get instruction with delay slot.
- MachineBasicBlock::instr_iterator DSI(I);
+ MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
- if (InMicroMipsMode && TII->GetInstSizeInBytes(&*std::next(DSI)) == 2 &&
+ if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 &&
DSI->isCall()) {
// If instruction in delay slot is 16b change opcode to
// corresponding instruction with short delay slot.
@@ -692,7 +692,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo();
unsigned Opcode = (*Slot).getOpcode();
- if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*CurrI)) == 2 &&
+ if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 &&
(Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
Opcode == Mips::PseudoReturn))
continue;
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