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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 21:08:22 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 21:08:22 +0000 |
| commit | 6781fc1648ac5ab6e92f304706139702413d5984 (patch) | |
| tree | 42154d2e3d2cfd0d335f1012b4371e04bc09f21a /llvm/lib/Target/Mips/MipsDSPInstrInfo.td | |
| parent | 8d5e128bd48a9c481150251c9761ce7838e65e87 (diff) | |
| download | bcm5719-llvm-6781fc1648ac5ab6e92f304706139702413d5984.tar.gz bcm5719-llvm-6781fc1648ac5ab6e92f304706139702413d5984.zip | |
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
llvm-svn: 188830
Diffstat (limited to 'llvm/lib/Target/Mips/MipsDSPInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td index 5020aa3fc0f..53e3389c2ee 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td @@ -1242,12 +1242,12 @@ def PREPEND : PREPEND_ENC, PREPEND_DESC; // Pseudos. let isPseudo = 1, isCodeGenOnly = 1 in { // Pseudo instructions for loading and storing accumulator registers. - defm LOAD_ACC64DSP : LoadM<"", ACC64DSPOpnd>; - defm STORE_ACC64DSP : StoreM<"", ACC64DSPOpnd>; + def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>; + def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>; // Pseudos for loading and storing ccond field of DSP control register. - defm LOAD_CCOND_DSP : LoadM<"load_ccond_dsp", DSPCC>; - defm STORE_CCOND_DSP : StoreM<"store_ccond_dsp", DSPCC>; + def LOAD_CCOND_DSP : Load<"load_ccond_dsp", DSPCC>; + def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>; } // Pseudo CMP and PICK instructions. |
