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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 15:50:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 15:50:29 +0000 |
| commit | e3a676e9adba668a7da944766218e98dd4b2c10a (patch) | |
| tree | 632a983ae9fe72b635cf72262bf2e9a0cbe6dce3 /llvm/lib/Target/Mips/MipsCallLowering.h | |
| parent | 3260ef16bbdecc391d7da8fe3bbe19585f6ccb19 (diff) | |
| download | bcm5719-llvm-e3a676e9adba668a7da944766218e98dd4b2c10a.tar.gz bcm5719-llvm-e3a676e9adba668a7da944766218e98dd4b2c10a.zip | |
CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().
llvm-svn: 364191
Diffstat (limited to 'llvm/lib/Target/Mips/MipsCallLowering.h')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsCallLowering.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.h b/llvm/lib/Target/Mips/MipsCallLowering.h index 05c703b60bd..4eacb7c8dbe 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.h +++ b/llvm/lib/Target/Mips/MipsCallLowering.h @@ -34,39 +34,39 @@ public: ArrayRef<CallLowering::ArgInfo> Args); protected: - bool assignVRegs(ArrayRef<unsigned> VRegs, ArrayRef<CCValAssign> ArgLocs, + bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex, const EVT &VT); - void setLeastSignificantFirst(SmallVectorImpl<unsigned> &VRegs); + void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs); MachineIRBuilder &MIRBuilder; MachineRegisterInfo &MRI; private: - bool assign(unsigned VReg, const CCValAssign &VA, const EVT &VT); + bool assign(Register VReg, const CCValAssign &VA, const EVT &VT); virtual unsigned getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) = 0; - virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA, + virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA, const EVT &VT) = 0; - virtual void assignValueToAddress(unsigned ValVReg, + virtual void assignValueToAddress(Register ValVReg, const CCValAssign &VA) = 0; - virtual bool handleSplit(SmallVectorImpl<unsigned> &VRegs, + virtual bool handleSplit(SmallVectorImpl<Register> &VRegs, ArrayRef<CCValAssign> ArgLocs, - unsigned ArgLocsStartIndex, unsigned ArgsReg, + unsigned ArgLocsStartIndex, Register ArgsReg, const EVT &VT) = 0; }; MipsCallLowering(const MipsTargetLowering &TLI); bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, - ArrayRef<unsigned> VRegs) const override; + ArrayRef<Register> VRegs) const override; bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, - ArrayRef<unsigned> VRegs) const override; + ArrayRef<Register> VRegs) const override; bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, |

