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author | Amara Emerson <aemerson@apple.com> | 2019-09-03 21:42:28 +0000 |
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committer | Amara Emerson <aemerson@apple.com> | 2019-09-03 21:42:28 +0000 |
commit | fbaf425b790000810611c085a39ed1b81e7545fe (patch) | |
tree | 55b0ad073ffa48ae4cdab06b569108c45d77b2fb /llvm/lib/Target/Mips/MipsCallLowering.cpp | |
parent | ccb1862bc99d293c4b9f397651a8b76ad1efe900 (diff) | |
download | bcm5719-llvm-fbaf425b790000810611c085a39ed1b81e7545fe.tar.gz bcm5719-llvm-fbaf425b790000810611c085a39ed1b81e7545fe.zip |
[GlobalISel][CallLowering] Add support for splitting types according to calling conventions.
On AArch64, s128 types have to be split into s64 GPRs when passed as arguments.
This change adds the generic support in call lowering for dealing with multiple
registers, for incoming and outgoing args.
Support for splitting for return types not yet implemented.
Differential Revision: https://reviews.llvm.org/D66180
llvm-svn: 370822
Diffstat (limited to 'llvm/lib/Target/Mips/MipsCallLowering.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/MipsCallLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 86913653bee..0d0e446fee9 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -508,7 +508,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, for (auto &Arg : Info.OrigArgs) { if (!isSupportedType(Arg.Ty)) return false; - if (Arg.Flags.isByVal() || Arg.Flags.isSRet()) + if (Arg.Flags[0].isByVal() || Arg.Flags[0].isSRet()) return false; } @@ -641,7 +641,7 @@ void MipsCallLowering::subTargetRegTypeForCallingConv( F.getContext(), F.getCallingConv(), VT); for (unsigned i = 0; i < NumRegs; ++i) { - ISD::ArgFlagsTy Flags = Arg.Flags; + ISD::ArgFlagsTy Flags = Arg.Flags[0]; if (i == 0) Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL)); |