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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-31 01:38:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-31 01:38:47 +0000 |
| commit | 2a64598ef2ec4841dd48483dc368da034d80d933 (patch) | |
| tree | 158052ad93e61e7d7e8879f984057f9074e63fad /llvm/lib/Target/Mips/MipsCallLowering.cpp | |
| parent | 15df273eb45dc53669739bb33388a12c1dfce962 (diff) | |
| download | bcm5719-llvm-2a64598ef2ec4841dd48483dc368da034d80d933.tar.gz bcm5719-llvm-2a64598ef2ec4841dd48483dc368da034d80d933.zip | |
GlobalISel: Fix creating MMOs with align 0
llvm-svn: 352712
Diffstat (limited to 'llvm/lib/Target/Mips/MipsCallLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsCallLowering.cpp | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 4da88b35dd4..fd0f7921ba3 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -146,15 +146,18 @@ void IncomingValueHandler::assignValueToReg(unsigned ValVReg, unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) { + MachineFunction &MF = MIRBuilder.getMF(); unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; unsigned Offset = VA.getLocMemOffset(); - MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); int FI = MFI.CreateFixedObject(Size, Offset, true); MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); - MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOLoad, - Size, /* Alignment */ 0); + + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + unsigned Align = MinAlign(TFL->getStackAlignment(), Offset); + MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align); unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); MIRBuilder.buildFrameIndex(AddrReg, FI); @@ -220,6 +223,9 @@ void OutgoingValueHandler::assignValueToReg(unsigned ValVReg, unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA, MachineMemOperand *&MMO) { + MachineFunction &MF = MIRBuilder.getMF(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + LLT p0 = LLT::pointer(0, 32); LLT s32 = LLT::scalar(32); unsigned SPReg = MRI.createGenericVirtualRegister(p0); @@ -235,8 +241,8 @@ unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA, MachinePointerInfo MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; - MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOStore, - Size, /* Alignment */ 0); + unsigned Align = MinAlign(TFL->getStackAlignment(), Offset); + MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align); return AddrReg; } |
