[MIPS GlobalISel] Set operand order for G_MERGE and G_UNMERGE

Set operands order for G_MERGE_VALUES and G_UNMERGE_VALUES so
that least significant bits always go first, regardless of endianness.

Differential Revision: https://reviews.llvm.org/D54098

llvm-svn: 346305

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 4d070f9f523..c550fadf663 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -45,9 +45,9 @@ bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<unsigned> VRegs,
   return true;
 }
 
-void MipsCallLowering::MipsHandler::setMostSignificantFirst(
+void MipsCallLowering::MipsHandler::setLeastSignificantFirst(
     SmallVectorImpl<unsigned> &VRegs) {
-  if (MIRBuilder.getMF().getDataLayout().isLittleEndian())
+  if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
     std::reverse(VRegs.begin(), VRegs.end());
 }
 
@@ -181,7 +181,7 @@ bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
                                        unsigned ArgsReg) {
   if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
     return false;
-  setMostSignificantFirst(VRegs);
+  setLeastSignificantFirst(VRegs);
   MIRBuilder.buildMerge(ArgsReg, VRegs);
   return true;
 }
@@ -283,7 +283,7 @@ bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
                                        unsigned ArgLocsStartIndex,
                                        unsigned ArgsReg) {
   MIRBuilder.buildUnmerge(VRegs, ArgsReg);
-  setMostSignificantFirst(VRegs);
+  setLeastSignificantFirst(VRegs);
   if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
     return false;