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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-01-25 01:43:36 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-01-25 01:43:36 +0000 |
commit | ff36fd3de3fb913f0b0f7ebff037a684f1848a4b (patch) | |
tree | 4e01072d15a4176cce7f1d77eb1ada207eb96b9b /llvm/lib/Target/Mips/MipsAnalyzeImmediate.h | |
parent | f41385f9bee0240982ec0d20785548003522de53 (diff) | |
download | bcm5719-llvm-ff36fd3de3fb913f0b0f7ebff037a684f1848a4b.tar.gz bcm5719-llvm-ff36fd3de3fb913f0b0f7ebff037a684f1848a4b.zip |
Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
load an immediate.
llvm-svn: 148900
Diffstat (limited to 'llvm/lib/Target/Mips/MipsAnalyzeImmediate.h')
-rw-r--r-- | llvm/lib/Target/Mips/MipsAnalyzeImmediate.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsAnalyzeImmediate.h b/llvm/lib/Target/Mips/MipsAnalyzeImmediate.h new file mode 100644 index 00000000000..fe181d8d342 --- /dev/null +++ b/llvm/lib/Target/Mips/MipsAnalyzeImmediate.h @@ -0,0 +1,62 @@ +//===-- MipsAnalyzeImmediate.h - Analyze immediates -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +#ifndef MIPS_ANALYZE_IMMEDIATE_H +#define MIPS_ANALYZE_IMMEDIATE_H + +#include "llvm/ADT/SmallVector.h" + +namespace llvm { + + class MipsAnalyzeImmediate { + public: + struct Inst { + unsigned Opc, ImmOpnd; + Inst(unsigned Opc, unsigned ImmOpnd); + }; + typedef SmallVector<Inst, 7 > InstSeq; + + /// Analyze - Get an instrucion sequence to load immediate Imm. The last + /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is + /// true; + const InstSeq &Analyze(int64_t Imm, unsigned Size, bool LastInstrIsADDiu); + private: + typedef SmallVector<InstSeq, 5> InstSeqLs; + + /// AddInstr - Add I to all instruction sequences in SeqLs. + void AddInstr(InstSeqLs &SeqLs, const Inst &I); + + /// GetInstSeqLsADDiu - Get instrucion sequences which end with an ADDiu to + /// load immediate Imm + void GetInstSeqLsADDiu(int64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + + /// GetInstSeqLsORi - Get instrucion sequences which end with an ORi to + /// load immediate Imm + void GetInstSeqLsORi(int64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + + /// GetInstSeqLsSLL - Get instrucion sequences which end with a SLL to + /// load immediate Imm + void GetInstSeqLsSLL(int64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + + /// GetInstSeqLs - Get instrucion sequences to load immediate Imm. + void GetInstSeqLs(int64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + + /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. + void ReplaceADDiuSLLWithLUi(InstSeq &Seq); + + /// GetShortestSeq - Find the shortest instruction sequence in SeqLs and + /// return it in Insts. + void GetShortestSeq(InstSeqLs &SeqLs, InstSeq &Insts); + + unsigned Size; + unsigned ADDiu, ORi, SLL, LUi; + InstSeq Insts; + }; +} + +#endif |