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authorReed Kotler <rkotler@mips.com>2013-05-21 22:06:02 +0000
committerReed Kotler <rkotler@mips.com>2013-05-21 22:06:02 +0000
commitc6c7e4a67cf02e9daec3a7071fd50bcf0cb59d82 (patch)
tree049fb12ffc4e8a74c69bef593d84b3eb07f1503e /llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
parentfc2f7a53f7a78806545903cb7583cc12c6e9a45b (diff)
downloadbcm5719-llvm-c6c7e4a67cf02e9daec3a7071fd50bcf0cb59d82.tar.gz
bcm5719-llvm-c6c7e4a67cf02e9daec3a7071fd50bcf0cb59d82.zip
Mips16 does not use register scavenger from TargetRegisterInfo. It allocates
a RegScavenger object on it's own. llvm-svn: 182430
Diffstat (limited to 'llvm/lib/Target/Mips/Mips16RegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/Mips/Mips16RegisterInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
index 7ad18f2b4d9..4756b1e84dc 100644
--- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
@@ -47,11 +47,11 @@ Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST,
bool Mips16RegisterInfo::requiresRegisterScavenging
(const MachineFunction &MF) const {
- return true;
+ return false;
}
bool Mips16RegisterInfo::requiresFrameIndexScavenging
(const MachineFunction &MF) const {
- return true;
+ return false;
}
bool Mips16RegisterInfo::useFPForScavengingIndex
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