Fixed features usage.

llvm-svn: 53277

1 files changed, 12 insertions, 10 deletions

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 1199cc47ace..bb83fc07c20 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -33,20 +33,22 @@ def MipsInstrInfo : InstrInfo {
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
-def FeatureGP64Bit      : SubtargetFeature<"gp64", "IsGP64bit", "true",
+def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
-def FeatureFP64Bit      : SubtargetFeature<"fp64", "IsFP64bit", "true",
+def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
                                 "Support 64-bit FP registers.">;
-def FeatureSingleFloat  : SubtargetFeature<"single-float", "IsSingleFloat",
+def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
-def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU", 
-                                "true", "Enable Allegrex VFPU instructions.">;
-def FeatureMips2        : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
+def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
                                 "Mips2 ISA Support">;
-def FeatureO32          : SubtargetFeature<"o32", "MipsABI", "O32",
+def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
                                 "Enable o32 ABI">;
-def FeatureEABI         : SubtargetFeature<"eabi", "MipsABI", "EABI",
+def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
                                 "Enable eabi ABI">;
+def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU", 
+                                "true", "Enable vector FPU instructions.">;
+def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true", 
+                                "Enable 'signext in register' instructions.">;
 
 //===----------------------------------------------------------------------===//
 // Mips processors supported.
@@ -64,8 +66,8 @@ def : Proc<"r6000", [FeatureMips2]>;
 
 // Allegrex is a 32bit subset of r4000, both for interger and fp registers, 
 // but much more similar to Mips2 than Mips3. 
-def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU,
-                        FeatureEABI]>;
+def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, 
+                        FeatureSEInReg, FeatureVFPU]>;
 
 def Mips : Target {
   let InstructionSet = MipsInstrInfo;