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authorZlatko Buljan <Zlatko.Buljan@imgtec.com>2015-10-15 08:59:45 +0000
committerZlatko Buljan <Zlatko.Buljan@imgtec.com>2015-10-15 08:59:45 +0000
commit54b1eb4c734e19a352e2128a9dfea281e9734f58 (patch)
treea4f9146e473f29987c7f6f5dc2914e87a31a9a09 /llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
parent3a3c4b8a39a56f33357cc0837f244dfbb7876bbb (diff)
downloadbcm5719-llvm-54b1eb4c734e19a352e2128a9dfea281e9734f58.tar.gz
bcm5719-llvm-54b1eb4c734e19a352e2128a9dfea281e9734f58.zip
[mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions
Differential Revision: http://reviews.llvm.org/D13376 llvm-svn: 250382
Diffstat (limited to 'llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td')
-rw-r--r--llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td25
1 files changed, 22 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
index e107de87e64..77049609295 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -12,8 +12,27 @@
//===----------------------------------------------------------------------===//
// Instruction encoding.
-class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>;
+class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
+class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>;
+class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>;
+class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>;
+class DPAQX_S_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_s.w.ph", 0b10001010>;
+class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_sa.w.ph", 0b11001010>;
+class DPAU_H_QBL_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbl", 0b10000010>;
+class DPAU_H_QBR_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbr", 0b11000010>;
+class DPAX_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpax.w.ph", 0b01000010>;
// Instruction defs.
-// MIPS DSP Rev 1
-def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS;
+// microMIPS DSP Rev 1
+def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
+def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC;
+def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC;
+def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC;
+def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC;
+// microMIPS DSP Rev 2
+def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
+def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
+ ISA_DSPR2;
+def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
+ ISA_DSPR2;
+def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
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