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| author | Jack Carter <jack.carter@imgtec.com> | 2013-08-13 20:19:16 +0000 |
|---|---|---|
| committer | Jack Carter <jack.carter@imgtec.com> | 2013-08-13 20:19:16 +0000 |
| commit | 9770097727c21d41fe966e7faef69140a72a49b7 (patch) | |
| tree | 4a3378bd0ca7a5a4552455a7c110d591f69e80fe /llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | |
| parent | 1be0c73a94c4eb86bc173821a2a4da2d52b9c156 (diff) | |
| download | bcm5719-llvm-9770097727c21d41fe966e7faef69140a72a49b7.tar.gz bcm5719-llvm-9770097727c21d41fe966e7faef69140a72a49b7.zip | |
[Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
llvm-svn: 188312
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index d019f05f8b4..aa927bd77b0 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -97,6 +97,8 @@ public: unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const; unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, @@ -212,6 +214,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, LowerDextDins(TmpInst); } + unsigned long N = Fixups.size(); uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups); // Check for unimplemented opcodes. @@ -224,6 +227,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, if (STI.getFeatureBits() & Mips::FeatureMicroMips) { int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); if (NewOpcode != -1) { + if (Fixups.size() > N) + Fixups.pop_back(); Opcode = NewOpcode; TmpInst.setOpcode (NewOpcode); Binary = getBinaryCodeForInstr(TmpInst, Fixups); @@ -417,6 +422,17 @@ MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, return (OffBits & 0xFFFF) | RegBits; } +unsigned MipsMCCodeEmitter:: +getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const { + // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. + assert(MI.getOperand(OpNo).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); + + return (OffBits & 0x0FFF) | RegBits; +} + unsigned MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const { |
