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author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2015-10-16 12:24:58 +0000 |
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committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2015-10-16 12:24:58 +0000 |
commit | 3c88fbd3673b3d50fbf2fce44e8b623cbbca301f (patch) | |
tree | 0472bcd71f264854d9312e803191af08b131b86f /llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | |
parent | 1487a3de409f10db25c6c19441413393863bb346 (diff) | |
download | bcm5719-llvm-3c88fbd3673b3d50fbf2fce44e8b623cbbca301f.tar.gz bcm5719-llvm-3c88fbd3673b3d50fbf2fce44e8b623cbbca301f.zip |
[mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions
Differential Revision: http://reviews.llvm.org/D11633
llvm-svn: 250511
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 1d06860bdf9..bd6afcb1fe1 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -773,7 +773,7 @@ getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, return OffBits & 0x7F; } - unsigned MipsMCCodeEmitter:: +unsigned MipsMCCodeEmitter:: getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { @@ -810,6 +810,19 @@ getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, } unsigned MipsMCCodeEmitter:: +getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. + assert(MI.getOperand(OpNo).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, + STI) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); + + return (OffBits & 0xFFFF) | RegBits; +} + +unsigned MipsMCCodeEmitter:: getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { |