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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-06-12 12:40:00 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-06-12 12:40:00 +0000 |
| commit | b9c07f3b866f90e56f323adb4e6e8cbf3a94292b (patch) | |
| tree | ef07ab9439714e5acf67750d29fa65c34d728135 /llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | |
| parent | ed6882b8351b37c07b3ddc51e1a62d7d96135aaa (diff) | |
| download | bcm5719-llvm-b9c07f3b866f90e56f323adb4e6e8cbf3a94292b.tar.gz bcm5719-llvm-b9c07f3b866f90e56f323adb4e6e8cbf3a94292b.zip | |
[mips][mips64r6] Add R_MIPS_PC19_S2
Differential Revision: http://reviews.llvm.org/D3866
llvm-svn: 210773
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 5375a00fd11..ea8ab4d309c 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -70,6 +70,13 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, if (!isIntN(16, Value) && Ctx) Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); break; + case Mips::fixup_MIPS_PC19_S2: + // Forcing a signed division because Value can be negative. + Value = (int64_t)Value / 4; + // We now check if Value can be encoded as a 19-bit signed immediate. + if (!isIntN(19, Value) && Ctx) + Ctx->FatalError(Fixup.getLoc(), "out of range PC19 fixup"); + break; case Mips::fixup_Mips_26: // So far we are only using this type for jumps. // The displacement is then divided by 4 to give us an 28 bit @@ -247,6 +254,7 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_Mips_GOT_LO16", 0, 16, 0 }, { "fixup_Mips_CALL_HI16", 0, 16, 0 }, { "fixup_Mips_CALL_LO16", 0, 16, 0 }, + { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, @@ -308,6 +316,7 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_Mips_GOT_LO16", 16, 16, 0 }, { "fixup_Mips_CALL_HI16", 16, 16, 0 }, { "fixup_Mips_CALL_LO16", 16, 16, 0 }, + { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, |
