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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-10-15 14:34:23 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-10-15 14:34:23 +0000 |
| commit | 8008de55515f7e1eba8992f87aa2db0eccfd78fe (patch) | |
| tree | 43934649f610e4d6a0178f520fd1d235f3f9df6b /llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp | |
| parent | 5dfcda73d538728812fda0ce5b0025f490fd3c6c (diff) | |
| download | bcm5719-llvm-8008de55515f7e1eba8992f87aa2db0eccfd78fe.tar.gz bcm5719-llvm-8008de55515f7e1eba8992f87aa2db0eccfd78fe.zip | |
[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.
Summary:
The -mcpu=mips16 option caused the Integrated Assembler to crash because
it couldn't figure out the architecture revision number to write to the
.MIPS.abiflags section. This CPU definition has been removed because, like
microMIPS, MIPS16 is an ASE to a base architecture.
Reviewers: vkalintiris
Subscribers: rkotler, llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D13656
llvm-svn: 250407
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp index 056cf754dc2..cdcc3923b81 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp @@ -78,7 +78,6 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU, .Case("mips32r3", MipsABIInfo::O32()) .Case("mips32r5", MipsABIInfo::O32()) .Case("mips32r6", MipsABIInfo::O32()) - .Case("mips16", MipsABIInfo::O32()) .Case("mips3", MipsABIInfo::N64()) .Case("mips4", MipsABIInfo::N64()) .Case("mips5", MipsABIInfo::N64()) |
