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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-02-10 16:36:20 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-02-10 16:36:20 +0000 |
| commit | 416886793f68a088dd5903caff5f720dd307bfdb (patch) | |
| tree | 20f5a38526addde245e9f0714d6155ada4db491c /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | 8ce4a069e410863a79c58616a6e0cc5c5077739d (diff) | |
| download | bcm5719-llvm-416886793f68a088dd5903caff5f720dd307bfdb.tar.gz bcm5719-llvm-416886793f68a088dd5903caff5f720dd307bfdb.zip | |
[mips][microMIPS] Implement movep instruction
Differential Revision: http://reviews.llvm.org/D7465
llvm-svn: 228703
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 267f2d41c1a..c8a5195e8e6 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -114,6 +114,11 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -439,6 +444,10 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + namespace llvm { extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, TheMips64elTarget; @@ -1005,6 +1014,17 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::CreateReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -1835,6 +1855,51 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, return MCDisassembler::Success; } +static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + + unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + + switch (RegPair) { + default: + return MCDisassembler::Fail; + case 0: + Inst.addOperand(MCOperand::CreateReg(Mips::A1)); + Inst.addOperand(MCOperand::CreateReg(Mips::A2)); + break; + case 1: + Inst.addOperand(MCOperand::CreateReg(Mips::A1)); + Inst.addOperand(MCOperand::CreateReg(Mips::A3)); + break; + case 2: + Inst.addOperand(MCOperand::CreateReg(Mips::A2)); + Inst.addOperand(MCOperand::CreateReg(Mips::A3)); + break; + case 3: + Inst.addOperand(MCOperand::CreateReg(Mips::A0)); + Inst.addOperand(MCOperand::CreateReg(Mips::S5)); + break; + case 4: + Inst.addOperand(MCOperand::CreateReg(Mips::A0)); + Inst.addOperand(MCOperand::CreateReg(Mips::S6)); + break; + case 5: + Inst.addOperand(MCOperand::CreateReg(Mips::A0)); + Inst.addOperand(MCOperand::CreateReg(Mips::A1)); + break; + case 6: + Inst.addOperand(MCOperand::CreateReg(Mips::A0)); + Inst.addOperand(MCOperand::CreateReg(Mips::A2)); + break; + case 7: + Inst.addOperand(MCOperand::CreateReg(Mips::A0)); + Inst.addOperand(MCOperand::CreateReg(Mips::A3)); + break; + } + + return MCDisassembler::Success; +} + static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2)); |
