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authorAkira Hatanaka <ahatanaka@mips.com>2013-08-20 22:58:56 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-08-20 22:58:56 +0000
commit14e31a2fe77498ea5d0ccc44d9618aa22c9db812 (patch)
treebee8643da49729b9fa9f21030ce4d83d8ec8024a /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
parent906e48f2a0a5bef36145243f6ce4269f1e35a89b (diff)
downloadbcm5719-llvm-14e31a2fe77498ea5d0ccc44d9618aa22c9db812.tar.gz
bcm5719-llvm-14e31a2fe77498ea5d0ccc44d9618aa22c9db812.zip
[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. llvm-svn: 188842
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
-rw-r--r--llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp17
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 1f2d210a84a..c6f3babec9b 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -118,6 +118,11 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@@ -390,6 +395,18 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
+ Inst.addOperand(MCOperand::CreateReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
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