[mips] Fix loading "double" immediate into a GPR and FPR

If a "double" (64-bit) value has zero low 32-bits, it's possible to load
such value into a GP/FP registers as an instruction immediate. But now
assembler loads only high 32-bits of the value.

For example, if a target register is GPR the `li.d $4, 1.0` instruction
converts into the `lui $4, 16368` one. As a result, we get `0x3FF00000`
in the register. While a correct representation of the `1.0` value is
`0x3FF0000000000000`. The patch fixes that.

Differential Revision: https://reviews.llvm.org/D68776

llvm-svn: 374544

1 files changed, 14 insertions, 6 deletions

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8d567d42b96..51bcf798182 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3403,8 +3403,8 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
 
   if (LoImmOp64 == 0) {
     if (isABI_N32() || isABI_N64()) {
-      if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true,
-                        IDLoc, Out, STI))
+      if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, true, IDLoc,
+                        Out, STI))
         return true;
     } else {
       if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,
@@ -3477,12 +3477,20 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
       !((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
     // FIXME: In the case where the constant is zero, we can load the
     // register directly from the zero register.
-    if (loadImmediate(HiImmOp64, TmpReg, Mips::NoRegister, true, true, IDLoc,
+
+    if (isABI_N32() || isABI_N64()) {
+      if (loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
+                        Out, STI))
+        return true;
+      TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
+      return false;
+    }
+
+    if (loadImmediate(HiImmOp64, TmpReg, Mips::NoRegister, true, false, IDLoc,
                       Out, STI))
       return true;
-    if (isABI_N32() || isABI_N64())
-      TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
-    else if (hasMips32r2()) {
+
+    if (hasMips32r2()) {
       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
       TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
     } else {