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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-10-12 07:42:44 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-10-12 07:42:44 +0000 |
| commit | 4a46af845f6753b33d7c943ae4cc1f945b5ea211 (patch) | |
| tree | 512ac255f95774c67bb1d4f5f964011ece2de006 /llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | |
| parent | fe88be8c3af9523b887368e91fbc56968e06d8a5 (diff) | |
| download | bcm5719-llvm-4a46af845f6753b33d7c943ae4cc1f945b5ea211.tar.gz bcm5719-llvm-4a46af845f6753b33d7c943ae4cc1f945b5ea211.zip | |
[mips] Fix `loadImmediate` calls when load non-address values.
llvm-svn: 374640
Diffstat (limited to 'llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 86f50185c2d..5ce86943ed3 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3324,7 +3324,7 @@ bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, uint32_t ImmOp32 = covertDoubleImmToSingleImm(convertIntToDoubleImm(ImmOp64)); - return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc, + return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, Out, STI); } @@ -3397,15 +3397,15 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, if (Lo_32(ImmOp64) == 0) { if (isABI_N32() || isABI_N64()) { - if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, true, IDLoc, - Out, STI)) + if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, + IDLoc, Out, STI)) return true; } else { - if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, true, + if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, IDLoc, Out, STI)) return true; - if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true, + if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, IDLoc, Out, STI)) return true; } |

