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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-03-14 11:16:56 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-03-14 11:16:56 +0000 |
commit | 19b7f76afa319151ac697a7adf9ab12bc52fecfd (patch) | |
tree | 6ed33e94ad319a10b8d6f632a4df7f0618f73986 /llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | |
parent | 369ebfe4c9c6526a981e85df87453bb1bc818df6 (diff) | |
download | bcm5719-llvm-19b7f76afa319151ac697a7adf9ab12bc52fecfd.tar.gz bcm5719-llvm-19b7f76afa319151ac697a7adf9ab12bc52fecfd.zip |
[mips] Range check uimm6_lsl2.
Summary:
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D17291
llvm-svn: 263419
Diffstat (limited to 'llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp')
-rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 86521de614c..cc54f1d57f6 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1855,16 +1855,6 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, ((Imm % 4 == 0) && Imm < 28 && Imm > 0))) return Error(IDLoc, "immediate operand value out of range"); break; - case Mips::ADDIUR1SP_MM: - Opnd = Inst.getOperand(1); - if (!Opnd.isImm()) - return Error(IDLoc, "expected immediate operand kind"); - Imm = Opnd.getImm(); - if (OffsetToAlignment(Imm, 4LL)) - return Error(IDLoc, "misaligned immediate operand value"); - if (Imm < 0 || Imm > 255) - return Error(IDLoc, "immediate operand value out of range"); - break; case Mips::ANDI16_MM: Opnd = Inst.getOperand(2); if (!Opnd.isImm()) @@ -3765,6 +3755,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_UImm6_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate"); + case Match_UImm6_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected both 8-bit unsigned immediate and multiple of 4"); case Match_SImm6_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit signed immediate"); |