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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 23:45:26 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 23:45:26 +0000 |
| commit | b1a4d9da3b7d48c40e6abee2acc9f6324dad7f84 (patch) | |
| tree | 9c40c9ccfbe5f8ef21d580220db6d0f82ec1764d /llvm/lib/Target/MSP430 | |
| parent | ee9143acf503e487f62423594ce52525e28ced9f (diff) | |
| download | bcm5719-llvm-b1a4d9da3b7d48c40e6abee2acc9f6324dad7f84.tar.gz bcm5719-llvm-b1a4d9da3b7d48c40e6abee2acc9f6324dad7f84.zip | |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
llvm-svn: 183061
Diffstat (limited to 'llvm/lib/Target/MSP430')
| -rw-r--r-- | llvm/lib/Target/MSP430/MSP430RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td index 07619d0675b..4010781a860 100644 --- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td @@ -43,7 +43,7 @@ def R13B : MSP430Reg<13, "r13">; def R14B : MSP430Reg<14, "r14">; def R15B : MSP430Reg<15, "r15">; -def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } +def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } let SubRegIndices = [subreg_8bit] in { def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; |
