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authorAnton Korobeynikov <asl@math.spbu.ru>2010-01-15 01:29:49 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2010-01-15 01:29:49 +0000
commitcefa7addc88b8f34501fd23250dca5772ef9f594 (patch)
tree2410d8732619441b09b0359f44737bb5d9c14282 /llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
parent89880c82247782e8becb7898f41d2fa48f4b1a35 (diff)
downloadbcm5719-llvm-cefa7addc88b8f34501fd23250dca5772ef9f594.tar.gz
bcm5719-llvm-cefa7addc88b8f34501fd23250dca5772ef9f594.zip
Fix cmp emission on msp430: we definitely should turn stuff like
"icmp lhs, rhs" into "cmp rhs, lhs". This should fix PR5979. llvm-svn: 93496
Diffstat (limited to 'llvm/lib/Target/MSP430/MSP430ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/MSP430/MSP430ISelLowering.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index eedc568bd7b..d3dce4b4ba2 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -660,16 +660,16 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
default: llvm_unreachable("Invalid integer condition!");
case ISD::SETEQ:
TCC = MSP430CC::COND_E; // aka COND_Z
- // Minor optimization: if RHS is a constant, swap operands, then the
+ // Minor optimization: if LHS is a constant, swap operands, then the
// constant can be folded into comparison.
- if (RHS.getOpcode() == ISD::Constant)
+ if (LHS.getOpcode() == ISD::Constant)
std::swap(LHS, RHS);
break;
case ISD::SETNE:
TCC = MSP430CC::COND_NE; // aka COND_NZ
- // Minor optimization: if RHS is a constant, swap operands, then the
+ // Minor optimization: if LHS is a constant, swap operands, then the
// constant can be folded into comparison.
- if (RHS.getOpcode() == ISD::Constant)
+ if (LHS.getOpcode() == ISD::Constant)
std::swap(LHS, RHS);
break;
case ISD::SETULE:
@@ -1014,8 +1014,8 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
// BB:
// cmp 0, N
// je RemBB
- BuildMI(BB, dl, TII.get(MSP430::CMP8ir))
- .addImm(0).addReg(ShiftAmtSrcReg);
+ BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
+ .addReg(ShiftAmtSrcReg).addImm(0);
BuildMI(BB, dl, TII.get(MSP430::JCC))
.addMBB(RemBB)
.addImm(MSP430CC::COND_E);
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