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authorAnton Korobeynikov <asl@math.spbu.ru>2009-10-11 19:14:21 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-10-11 19:14:21 +0000
commit6bce6bbf40eadc7e1521c44f3118e4f6f0cef560 (patch)
treeedc8c5574570396670e65c614cce3add7de2f133 /llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
parenta58a3f930a023ccd7e083e5ec4e90d55c8bc246d (diff)
downloadbcm5719-llvm-6bce6bbf40eadc7e1521c44f3118e4f6f0cef560.tar.gz
bcm5719-llvm-6bce6bbf40eadc7e1521c44f3118e4f6f0cef560.zip
Implement 'm' memory operand properly
llvm-svn: 83785
Diffstat (limited to 'llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index 25287e9dcec..a603e07b02e 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -52,6 +52,10 @@ namespace {
return "MSP430 DAG->DAG Pattern Instruction Selection";
}
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+ std::vector<SDValue> &OutOps);
+
// Include the pieces autogenerated from the target description.
#include "MSP430GenDAGISel.inc"
@@ -122,6 +126,22 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
}
+bool MSP430DAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+ std::vector<SDValue> &OutOps) {
+ SDValue Op0, Op1;
+ switch (ConstraintCode) {
+ default: return true;
+ case 'm': // memory
+ if (!SelectAddr(Op, Op, Op0, Op1))
+ return true;
+ break;
+ }
+
+ OutOps.push_back(Op0);
+ OutOps.push_back(Op1);
+ return false;
+}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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