Switch the MachineOperand accessors back to the short names like

isReg, etc., from isRegister, etc.

llvm-svn: 57006

4 files changed, 11 insertions, 11 deletions

diff --git a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
index a2c87462db7..3a44b46e976 100644
--- a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -91,7 +91,7 @@ namespace {
 // pool entries aren't immediates at this stage, so we check here.
 // If it's an immediate, print it the old fashioned way. If it's
 // not, we print it as a constant pool index.
-      if(MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         O << (int64_t)MI->getOperand(OpNo).getImm();
       } else { // this is a constant pool reference: FIXME: assert this
         printOp(MI->getOperand(OpNo));
diff --git a/llvm/lib/Target/IA64/IA64Bundling.cpp b/llvm/lib/Target/IA64/IA64Bundling.cpp
index c5bc83e134b..ebf93b9d1ac 100644
--- a/llvm/lib/Target/IA64/IA64Bundling.cpp
+++ b/llvm/lib/Target/IA64/IA64Bundling.cpp
@@ -84,7 +84,7 @@ bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
 
     for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
       MachineOperand &MO=CurrentInsn->getOperand(i);
-      if(MO.isRegister()) {
+      if (MO.isReg()) {
         if(MO.isUse()) { // TODO: exclude p0
           CurrentReads.insert(MO.getReg());
         }
diff --git a/llvm/lib/Target/IA64/IA64InstrInfo.cpp b/llvm/lib/Target/IA64/IA64InstrInfo.cpp
index 54bcce13c54..a9dce854521 100644
--- a/llvm/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/llvm/lib/Target/IA64/IA64InstrInfo.cpp
@@ -31,11 +31,11 @@ bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
   if (oc == IA64::MOV || oc == IA64::FMOV) {
   // TODO: this doesn't detect predicate moves
      assert(MI.getNumOperands() >= 2 &&
-             /* MI.getOperand(0).isRegister() &&
-             MI.getOperand(1).isRegister() && */
+             /* MI.getOperand(0).isReg() &&
+             MI.getOperand(1).isReg() && */
              "invalid register-register move instruction");
-     if( MI.getOperand(0).isRegister() &&
-         MI.getOperand(1).isRegister() ) {
+     if (MI.getOperand(0).isReg() &&
+         MI.getOperand(1).isReg()) {
        // if both operands of the MOV/FMOV are registers, then
        // yes, this is a move instruction
        sourceReg = MI.getOperand(1).getReg();
@@ -122,9 +122,9 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -174,9 +174,9 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
index a0bc9f860d4..952b3f48e99 100644
--- a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -121,7 +121,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 
   bool FP = hasFP(MF);
 
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }