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| author | Dale Johannesen <dalej@apple.com> | 2008-09-04 00:47:13 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2008-09-04 00:47:13 +0000 |
| commit | da2d80688b68fd1667b74efc9f008b33c347c2a3 (patch) | |
| tree | 3a486fffb3ceb5b9182f365874a63b755ea4258f /llvm/lib/Target/IA64/IA64ISelLowering.cpp | |
| parent | 3cbb3b2920e6bb3ba7eac44c1f2165b022616ffe (diff) | |
| download | bcm5719-llvm-da2d80688b68fd1667b74efc9f008b33c347c2a3.tar.gz bcm5719-llvm-da2d80688b68fd1667b74efc9f008b33c347c2a3.zip | |
Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
llvm-svn: 55753
Diffstat (limited to 'llvm/lib/Target/IA64/IA64ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelLowering.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp index 9cd9ef0fb80..cdcacf3fd8e 100644 --- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp +++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp @@ -75,10 +75,20 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FLOG , MVT::f64, Expand); + setOperationAction(ISD::FLOG2, MVT::f64, Expand); + setOperationAction(ISD::FLOG10,MVT::f64, Expand); + setOperationAction(ISD::FEXP , MVT::f64, Expand); + setOperationAction(ISD::FEXP2, MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); setOperationAction(ISD::FPOW , MVT::f32, Expand); + setOperationAction(ISD::FLOG , MVT::f32, Expand); + setOperationAction(ISD::FLOG2, MVT::f32, Expand); + setOperationAction(ISD::FLOG10,MVT::f32, Expand); + setOperationAction(ISD::FEXP , MVT::f32, Expand); + setOperationAction(ISD::FEXP2, MVT::f32, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); |
