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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-08-28 18:36:21 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-08-28 18:36:21 +0000 |
| commit | 2164a271a333d4e822c95b977002d68f81c8c636 (patch) | |
| tree | ac8b28fdce40c1880c91b16ed491af72c64998ec /llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | |
| parent | 312c557b3b1d989faaf4437107cb8487bca6d515 (diff) | |
| download | bcm5719-llvm-2164a271a333d4e822c95b977002d68f81c8c636.tar.gz bcm5719-llvm-2164a271a333d4e822c95b977002d68f81c8c636.zip | |
[Hexagon] Check for potential bank conflicts in post-RA scheduling
Insert artificial edges between loads that could cause a cache bank
conflict.
llvm-svn: 311901
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index a6d134365a6..9b4530f2297 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -105,6 +105,7 @@ HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF, addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>()); addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>()); + addMutation(make_unique<HexagonSubtarget::BankConflictMutation>()); } // Check if FirstI modifies a register that SecondI reads. |
