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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-27 17:07:52 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-27 17:07:52 +0000 |
| commit | 0a15d241346c82938a07e818715a81cd30238694 (patch) | |
| tree | 2ebc2749cd8df70d44277946c52386f303fa32db /llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h | |
| parent | d058b882be1d5e540c8b5f9b5273913dd99ffc15 (diff) | |
| download | bcm5719-llvm-0a15d241346c82938a07e818715a81cd30238694.tar.gz bcm5719-llvm-0a15d241346c82938a07e818715a81cd30238694.zip | |
[Hexagon] Rudimentary support for auto-vectorization for HVX
This implements a set of TTI functions that the loop vectorizer uses.
The only purpose of this is to enable testing. Auto-vectorization is
disabled by default, enabled by -hexagon-autohvx.
llvm-svn: 328639
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h | 108 |
1 files changed, 107 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 58e23b2e1dc..7adacafa11c 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -70,6 +70,113 @@ public: /// @{ unsigned getNumberOfRegisters(bool vector) const; + unsigned getMaxInterleaveFactor(unsigned VF); + unsigned getRegisterBitWidth(bool Vector) const; + unsigned getMinVectorRegisterBitWidth() const; + + bool supportsEfficientVectorElementLoadStore() { + return false; + } + + unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) { + return 0; + } + + unsigned getOperandsScalarizationOverhead(ArrayRef<const Value*> Args, + unsigned VF) { + return 0; + } + + unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type*> Tys) { + return 1; + } + + unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, + ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF) { + return BaseT::getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF); + } + unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, + ArrayRef<Type*> Tys, FastMathFlags FMF, + unsigned ScalarizationCostPassed = UINT_MAX) { + return 1; + } + + bool hasBranchDivergence() { + return false; + } + + bool enableAggressiveInterleaving(bool LoopHasReductions) { + return false; + } + + unsigned getCFInstrCost(unsigned Opcode) { + return 1; + } + + unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *, + const SCEV *) { + return 0; + } + + unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace, const Instruction *I = nullptr); + + unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace) { + return 1; + } + + unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, + Type *SubTp) { + return 1; + } + + unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, + bool VariableMask, + unsigned Alignment) { + return 1; + } + + unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, + unsigned Factor, + ArrayRef<unsigned> Indices, + unsigned Alignment, + unsigned AddressSpace) { + return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, + Alignment, AddressSpace); + } + + unsigned getNumberOfParts(Type *Tp) { + return BaseT::getNumberOfParts(Tp); + } + + bool prefersVectorizedAddressing() { + return true; + } + + unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, + const Instruction *I) { + return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); + } + + unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, + TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, + TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, + TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, + TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, + ArrayRef<const Value *> Args = ArrayRef<const Value *>()) { + return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, + Opd1PropInfo, Opd2PropInfo, Args); + } + + unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + const Instruction *I = nullptr) { + return 1; + } + + unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { + return 1; + } /// @} @@ -80,5 +187,4 @@ public: }; } // end namespace llvm - #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H |

