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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-29 21:49:42 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-29 21:49:42 +0000 |
commit | f0b34a5c571ac3b748cc270b86ef59ad59b267bd (patch) | |
tree | 2be1eaf96f77729d03bd988070bf6489e0177c6d /llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp | |
parent | f396b4c40dad7df67f7cadc6aaa7ac3dbf42f866 (diff) | |
download | bcm5719-llvm-f0b34a5c571ac3b748cc270b86ef59ad59b267bd.tar.gz bcm5719-llvm-f0b34a5c571ac3b748cc270b86ef59ad59b267bd.zip |
[Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
llvm-svn: 277220
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 6dcac0dc7ee..89f0a1c4dcb 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -72,7 +72,7 @@ bool HexagonCallMutation::shouldTFRICallBind(const HexagonInstrInfo &HII, return false; // TypeXTYPE are 64 bit operations. - if (HII.getType(Inst2.getInstr()) == HexagonII::TypeXTYPE) + if (HII.getType(*Inst2.getInstr()) == HexagonII::TypeXTYPE) return true; return false; } @@ -168,7 +168,7 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { continue; // Enable .cur formation. - if (QII.mayBeCurLoad(Packet[i]->getInstr())) + if (QII.mayBeCurLoad(*Packet[i]->getInstr())) continue; for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(), @@ -616,7 +616,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (!SU || SU->isScheduled) return ResCount; - MachineInstr *Instr = SU->getInstr(); + MachineInstr &Instr = *SU->getInstr(); DEBUG(if (verbose) dbgs() << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); // Forced priority is high. @@ -705,7 +705,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, // available for it. auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>(); auto &QII = *QST.getInstrInfo(); - if (SU->isInstr() && QII.mayBeCurLoad(SU->getInstr())) { + if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) { if (Q.getID() == TopQID && Top.ResourceModel->isResourceAvailable(SU)) { ResCount += PriorityTwo; DEBUG(if (verbose) dbgs() << "C|"); @@ -744,11 +744,11 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, // Check for stalls in the previous packet. if (Q.getID() == TopQID) { for (auto J : Top.ResourceModel->OldPacket) - if (QII.producesStall(J->getInstr(), Instr)) + if (QII.producesStall(*J->getInstr(), Instr)) ResCount -= PriorityOne; } else { for (auto J : Bot.ResourceModel->OldPacket) - if (QII.producesStall(Instr, J->getInstr())) + if (QII.producesStall(Instr, *J->getInstr())) ResCount -= PriorityOne; } } @@ -841,8 +841,8 @@ pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker, const MachineInstr *CandI = Candidate.SU->getInstr(); const InstrItineraryData *InstrItins = QST.getInstrItineraryData(); - unsigned InstrLatency = QII.getInstrTimingClassLatency(InstrItins, MI); - unsigned CandLatency = QII.getInstrTimingClassLatency(InstrItins, CandI); + unsigned InstrLatency = QII.getInstrTimingClassLatency(InstrItins, *MI); + unsigned CandLatency = QII.getInstrTimingClassLatency(InstrItins, *CandI); DEBUG(dbgs() << "TC Tie Breaker Cand: " << CandLatency << " Instr:" << InstrLatency << "\n" << *MI << *CandI << "\n"); |