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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-07-15 20:16:03 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-07-15 20:16:03 +0000
commit6c715e1483cc2a21dd9d2076107d07b544538c89 (patch)
tree1b37dd797ae3e82dc975b4bb8e10a3a04535c68d /llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
parent188d2c34e6a212650e0111116291a03479cc7e2e (diff)
downloadbcm5719-llvm-6c715e1483cc2a21dd9d2076107d07b544538c89.tar.gz
bcm5719-llvm-6c715e1483cc2a21dd9d2076107d07b544538c89.zip
[Hexagon] Make MI scheduler check for stalls in previous packet on v60
Patch by Ikhlas Ajbar. llvm-svn: 275606
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp28
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
index 0cc02930fa1..2ff1b538f4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -105,6 +105,11 @@ void HexagonCallMutation::apply(ScheduleDAGInstrs *DAG) {
}
+/// Save the last formed packet
+void VLIWResourceModel::savePacket() {
+ OldPacket = Packet;
+}
+
/// Check if scheduling of this SU is possible
/// in the current packet.
/// It is _not_ precise (statefull), it is more like
@@ -155,6 +160,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
// Artificially reset state.
if (!SU) {
ResourcesModel->clearResources();
+ savePacket();
Packet.clear();
TotalPackets++;
return false;
@@ -163,6 +169,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
// start a new one.
if (!isResourceAvailable(SU)) {
ResourcesModel->clearResources();
+ savePacket();
Packet.clear();
TotalPackets++;
startNewCycle = true;
@@ -199,6 +206,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
// we start fresh.
if (Packet.size() >= SchedModel->getIssueWidth()) {
ResourcesModel->clearResources();
+ savePacket();
Packet.clear();
TotalPackets++;
startNewCycle = true;
@@ -552,6 +560,8 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
if (!SU || SU->isScheduled)
return ResCount;
+ MachineInstr *Instr = SU->getInstr();
+
// Forced priority is high.
if (SU->isScheduleHigh)
ResCount += PriorityOne;
@@ -596,6 +606,24 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
ResCount -= (Delta.Excess.getUnitInc()*PriorityTwo);
ResCount -= (Delta.CriticalMax.getUnitInc()*PriorityTwo);
+ auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
+ auto &QII = *QST.getInstrInfo();
+
+ // Give less preference to an instruction that will cause a stall with
+ // an instruction in the previous packet.
+ if (QII.isV60VectorInstruction(Instr)) {
+ // Check for stalls in the previous packet.
+ if (Q.getID() == TopQID) {
+ for (auto J : Top.ResourceModel->OldPacket)
+ if (QII.producesStall(J->getInstr(), Instr))
+ ResCount -= PriorityOne;
+ } else {
+ for (auto J : Bot.ResourceModel->OldPacket)
+ if (QII.producesStall(Instr, J->getInstr()))
+ ResCount -= PriorityOne;
+ }
+ }
+
DEBUG(if (verbose) dbgs() << " Total(" << ResCount << ")");
return ResCount;
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